1. Field of the Invention
The present invention relates to a semiconductor memory device and its control method that are preferable to be used when an input and output line (IO line) and the like, which output data and the like, are commonly used between banks.
2. Description of Related Art
In a dynamic random access memory (DRAM) having a plurality of banks, there are some cases in that a main input and output line (hereinbelow referred to as a MIO line), which inputs and outputs data from a memory cell to a peripheral circuit, is provided to each bank. The bank includes an address decoder, the memory cell array, a sense amplifier, and the like, and corresponds to a unit that is independently controlled in response to a command input from the external thereof. In addition, a plurality of local input and output lines (hereinbelow referred to as LIO lines), which inputs and outputs data to each memory cell via the sense amplifier and a bit line, connects with the MIO line.
In DRAM having a lot of MIO lines, if each bank is provided with the MIO line, the total number of the IO lines in a chip considerably increases, and the circuit line highly affects chip layout and space in DRAM that has a small storage capacity. In order to reduce the number of the MIO lines, the MIO line, which is provided with each bank, is commonly used between the banks. In this manner, a control of a bank unit is applied to a transistor and the like, which output data to the MIO line, and hence, a reduction in the number of the MIO lines is attempted.
On the other hand, in order to reduce testing cost, there are a lot of cases in that DRAM includes a circuit which achieves a parallel test (for example, refer to Japanese Unexamined Patent Application, First Publication, No. 2000-40397). In the parallel test, a lot of data are simultaneously written to a plurality of the memory cells from the limited MIO line, and then, the data is simultaneously read and compared with each other. Thereby, it can be simultaneously determined that a plurality of the memory cells correctly operates when the data is compared and agrees with each other. It can be said that the parallel test is an indispensable technology to DRAM at present.
There are a lot of technologies in which a parallel number of the parallel test is increased by simultaneously activating a plurality or all of the banks. However, in the above-mentioned circuit in which the same MIO line is commonly used by a plurality of the banks, the same MIO line is connected with a plurality of the banks. For this reason, a conflict of data output from each bank takes place in the same MIO line commonly used by a plurality of the banks, when a plurality of the banks are simultaneously activated so as to input and output data in the parallel test. Therefore, a control method is necessary to avoid the conflict of data in the parallel test of the chip in which the same MIO line is commonly used by a plurality of the banks. That is, for example, as shown in FIG. 7 to FIG. 9, each bank has to be operated in serial at a stage, in which data is output to an external data input and output line DQ after all the banks are simultaneously activated so as to input the data. When this serial operation is employed, testing time increases rather than the case operating in parallel entirely, so that the testing cost increases.
FIG. 7 and FIG. 8 show a typical example of a semiconductor memory device that includes 4 banks. More particularly, FIG. 7 shows a connecting condition of a normal operation mode, while FIG. 8 shows a connecting condition of a parallel test mode. FIG. 9 shows a timing chart of a read operation in the parallel test mode.
As shown in FIG. 7 and FIG. 8, 4 pieces of banks, or a bank 0 to a bank 3, which include a memory cell array and the like, are commonly provided with the 4 MIO lines. Each of the bank 0 to the bank 3 is provided with a bank array which includes a plurality of the LIO lines (unillustrated) connecting with each MIO line via transistors Tr 0 to Tr 3 and the like, a sense amplifier, a bit line, the memory cell, and the like.
The 2 MIO lines connect with a peripheral circuit 11 placed at a bank 0 side, and the other 2 MIO lines connect with a peripheral circuit 12 placed at a bank 3 side during the normal operation mode, as shown in FIG. 7. The peripheral circuits 11 and 12 include a main amplifier, a data latch circuit, and the like. The data is input and output to the memory cell in each of the bank 0 to the bank 3 via the peripheral circuit 11 or the peripheral circuit 12, by using the external data input and output line DQ (unillustrated).
On the other hand, all of the 4 MIO lines connect with a comparator circuit 21 during the parallel test mode, as shown in FIG. 8. After data is written in the banks for the test, the data is sequentially read out from each bank at a timing shown in FIG. 9. The data read to a plurality of the MIO lines is compared by the comparator circuit 21 for every adjacent memory mat. The compared result is output to the external data input and output line DQ in the serial operation. A clock signal, a command input from the outside, a variation of the data of the external data input and output line DQ are shown, from the top to the bottom in order, in FIG. 9. When a bank active command for all banks “ACT (All Bank)” followed by a read command for all the banks “Read (All Bank)” is input, the compared result of each of the bank 0 to the bank 3 is sequentially output to the external data input and output line DQ. After that, a precharge command for all the banks “PRE (All Bank)” is input, all the banks are precharged, and then, each bank is in an idle state.
As described above, when the parallel test, in which a signal of a plurality of data input and output lines is compared, is carried out, it is necessary to sequentially read the data from each bank in the serial operation in the semiconductor memory device in which a data input and output line, such as the MIO line or the like for at least outputting the data, is commonly used by a plurality of the banks. For this reason, the testing time increases due to the serial operation, and hence, there is a problem in that the testing cost increases.